Embodiments of the present disclosure relate to methods for manufacturing a semiconductor device, and more particularly, to methods for forming conductive film patterns or interconnection lines on a substrate using a screen printing technique.
A semiconductor package is used in a variety of products. According to the recent trend toward miniaturization and slimness of products, the size of a semiconductor package has decreased. In order to reduce the size of the semiconductor package, a flip chip package in which solder bumps are directly formed on a surface of a semiconductor die, or a through silicone via (TSV) package in which TSVs are formed on bonding pads of a semiconductor die and solder bumps are then formed on the TSVs, is being highlighted. The flip chip package or the TSV package generally includes a redistribution layer (RDL) that is connected to a bonding pad of a semiconductor die to redistribute a position where a solder bump is formed, and an under bump metal (UBM) that is connected to the RDL to increase an adhesive strength between the solder bump and the RDL.
Meanwhile, along with advances in semiconductor industry and users' demand, electronic devices are becoming smaller and lighter and semiconductor chip packages as essential components of the electronic devices are also becoming smaller and lighter accordingly. To cope with such trends, a package known as a chip stack package has been developed, in which a plurality of semiconductor chips are vertically stacked to implement a semiconductor chip package. The chip stack package is advantageous in achieving a smaller and lighter package in view of the size, weight and mounting area, compared to a case of using a plurality of unit semiconductor chip packages each having a built-in semiconductor chip. In the chip stack package, if an electrode or pad for signal transmission of a semiconductor chip is centrally positioned, it is difficult to directly connect the pad to a substrate through a wire. Thus, the pad is redistributed in a peripheral region of the chip using a redistribution layer (RDL) and then connected to the wire to complete the package. The RDL of the chip stack package is subjected to patterning processes, including plating, mask exposure, etching, and so on, to interconnect bonding pads, or a conductive material, such as silver (Ag) paste, is patterned using a printer to interconnect bonding pads. In order to secure patterning accuracy, however, it is necessary to use a high-priced equipment in the redistribution process, and the processing speed is low, unavoidably increasing the cost of the package.